Current mirror circuits of the type to which the present invention relates are widely used as basic building blocks in the design of linear analog integrated circuits. They may be employed as biasing elements, active loads (e.g., such as in amplifier stages) or as all-purpose current sources (e.g., such as bit current cells in analog-to-digital converters). Basic topologies for conventional current mirror circuits that have proven useful are the simple current mirror, Wilson mirror, enhanced Wilson mirror, Widlar mirror, cascode mirror and enhanced cascode mirror. A general background discussion of conventional mirrors is set forth in U.S. Pat. No. 5,311,115, the disclosure of which is incorporated herein by reference.
A current mirror is a current input/output device which, ideally, has zero input impedance and infinite output impedance, so that current output remains a fixed function of current input, regardless of variations in output load, variations in output voltage or fluctuations in applied power source. To achieve the desired large output impedance typically requires some form of cascoding or stacking of output devices, in order to multiply the output resistance available from a single device. The need to do this becomes increasingly more important, as process minimum geometries continue to shrink and output resistances of short channel length devices continue to drop. An undesirable side effect of cascoding, however, is that output voltage swing (range of output voltage for which the output resistance remains high) becomes limited due to the need to maintain additional series-connected devices in their desired (e.g., saturated for MOS devices) operating regions. This problem of loss of voltage range is further compounded by a trend toward lower voltage power supplies in small geometry processes. For example, losing 1.25 volts of output range can be significant, resulting in total output swings of only 2.5 volts, where a 5.0 volt voltage supply is involved.
In addition to the above-referenced U.S. Pat. No. 5,311,115, general background information relating to current mirror circuits is also given in Gray & Meyer, Analysis and Design of Analog Integrated Circuits, Ch. 4 (1977 John Wiley & Sons) and Alvarez, BiCMOS Technology and Applications, Sec. 8.3 (1989 Kluwer Academic Publishers). And, though particular embodiments discussed herein are implemented utilizing N-channel MOS circuit technology, it should be understood that the same circuits may also be implemented utilizing complementary (viz. P-channel) devices or other (viz. bipolar or BiCMOS) technologies.
FIG. 1 illustrates a prior art simple current mirror 10 implemented using N-channel MOS transistors. The considerations surrounding a simple bipolar current mirror are similar and are discussed in the Gray & Meyer and Alvarez references noted above. In addition, various substrate connections are equally viable, though not explicitly drawn.
Ideally, the function of current mirror 10 is to match channel current I.sub.OUT through transistor T.sub.2 to channel current I.sub.IN through transistor T.sub.1, in order that current I.sub.OUT "mirrors" current I.sub.IN. Transistor T.sub.1 is diode-connected to place it in saturation, with V.sub.DS1 .gtoreq.V.sub.GS1. The gate of transistor T.sub.2 is connected to the gate of transistor T.sub.1, and the sources of transistors T.sub.1 and T.sub.2 are connected to a common voltage source (viz. ground), so that the gate-to-source voltages of transistors T.sub.1 and T.sub.2 are equal (V.sub.GS2 =V.sub.GS1). Therefore, when transistor T.sub.2 also operates in saturation, the channel current I.sub.OUT through transistor T.sub.2 is equal to some pre-established fixed multiple of channel current I.sub.IN through transistor T.sub.1. This is true for devices operating both above threshold (V.sub.GS .gtoreq.V.sub.T) and in the subthreshold region (V.sub.GS &lt;V.sub.T).
For transistors T.sub.1 and T.sub.2 formed on the same integrated circuit and having identical parameters, for V.sub.GS2 =V.sub.GS1, the output and input currents will be equal (I.sub.OUT =I.sub.IN). However, transistors T.sub.1 and T.sub.2 can be formed with different channel lengths and widths so that the currents I.sub.OUT and I.sub.IN will have a constant aspect ratio A.sub.i, which can be either less than or greater than unity, and which is defined by the relationship: ##EQU1## where W.sub.1 =channel width of transistor T.sub.1 ;
W.sub.2 =channel width of transistor T.sub.2 ; PA0 L.sub.1 =channel length of transistor T.sub.1 ; and PA0 L.sub.2 =channel length of transistor T.sub.2.
Thus, the task of selecting a desired current aspect ratio is simplified to selecting transistor geometry in accordance with Equation (1). Typically, L.sub.1 =L.sub.2 ; and, thus, the relationship can be simplified to: EQU A.sub.i =I.sub.OUT /I.sub.IN =W.sub.2 /W.sub.1 ( 2)
Ideally, the output current I.sub.OUT should remain constant for varying output loads and/or output voltages occurring at output terminal +V.sub.OUT. Thus, the higher the output resistance Rout of a current source, the more ideal it is. For simple current mirrors, output resistance R.sub.OUT is the same as the output resistance of the output rail transistors through which current I.sub.OUT flows (viz. transistor T.sub.2 in FIG. 1). Over a common range of values, output resistance is roughly proportional to channel length. Yet, although it is possible to achieve higher output resistance using longer channels, the parasitic pole frequency of the mirror will be lowered thereby. Also, unless the gate width is scaled proportionately, the gate-to-source voltage may become excessively large, increasing the requirements for saturation voltage. Output current I.sub.OUT may also fluctuate due to the fact that V.sub.DS1 is not necessarily equal to V.sub.DS2 and, thus, the modulation of drain current as the drain voltage varies causes a variation of I.sub.OUT.
Because of the importance of high output resistance, cascoding or stacking of transistors is often preferred. A conventional cascode current mirror 20 is shown in FIG. 2. Cascode current mirror 20 minimizes variations in I.sub.OUT /I.sub.IN due to output resistance R.sub.OUT. The cascode mirror 20 is characterized by the addition of a second mirrored pair of transistors T.sub.3 and T.sub.4, respectively connected between the first pair of transistors T.sub.1 and T.sub.2 and the input/output terminals, as shown. Again, for discussion purposes, the illustrative circuit is implemented using N-channel MOS elements; however, those skilled in the art to which the invention relates will appreciate that P-channel MOS device, as well as bipolar and BiCMOS, implementations are possible.
In circuit 20, transistor T.sub.3 is diode-connected to place it in saturation, with its drain connected to input terminal +V.sub.IN and its source connected to the drain of transistor T.sub.1. Transistor T.sub.4 has its drain connected to output terminal +V.sub.OUT and its source connected to the drain of transistor T.sub.2. With the gate of transistor T.sub.3 connected to the gate of transistor T.sub.4, current I.sub.IN flowing through transistors T.sub.1, T.sub.3 and current I.sub.OUT flowing through transistors T.sub.2, T.sub.4 are related in accordance with a fixed aspect ratio of transistors T.sub.1, T.sub.2, as for the simple mirror circuit 10 of FIG. 1. Cascode current mirror 20 is, in effect, a cascaded series of two current mirrors 10 of FIG. 1. And, assuming all operational parameters of transistors T.sub.1 through T.sub.4 are identical (i.e., the threshold voltages of the devices are identical and L.sub.1 =L.sub.2, L.sub.3 =L.sub.4, and W.sub.2 /W.sub.1 =W.sub.4 /W.sub.3), then drain voltage V.sub.D1 of transistor T.sub.1 will equal drain voltage V.sub.D2 of transistor T.sub.2. Thus, even though a voltage fluctuation may occur at the output terminal +V.sub.OUT which increases the drain voltage of transistor T.sub.4, the drain current I.sub.OUT through transistors T.sub.2 and T.sub.4 Will remain relatively constant. Current ratio I.sub.OUT /I.sub.IN is thus maintained, and cascode current mirror 20 minimizes variations in I.sub.OUT /I.sub.IN due to output resistance R.sub.OUT.
Thus, because of the higher output impedance, circuit 20 provides a strict current gain I.sub.OUT /I.sub.IN. It also has very good power supply rejection characteristics (ability to maintain constant output current, unaffected by input power supply noise) because transistors T.sub.1, T.sub.2 have identical gate voltages and very similar drain voltages. There is, however, a tradeoff for achieving a higher output impedance. With the simple current mirror 10, the minimum saturation voltage required for operation is merely the excess bias V.sub.D2, where V.sub.D2 =(V.sub.GS1 -V.sub.T1), and V.sub.D2 is the overdrive voltage above the threshold voltage V.sub.T1. Because of the additional series-connected transistors, however, a greater minimum saturation voltage is required for operation of the cascode current mirror 20 of FIG. 2. For the cascoded arrangement 20, transistor T.sub.4 leaves the saturation region of operation if output terminal voltage +V.sub.OUT drops below V.sub.G2 -V.sub.T4 (typically greater than 1.0 volts away from power supply voltage). This can severely limit available output voltage swing for low voltage power supplies.
FIG. 3 shows a conventional enhanced cascode mirror 30, which addresses the problem of the poor output voltage swing and is an attempt to simultaneously achieve high output resistance R.sub.OUT and a relatively low minimum saturation voltage. In this arrangement, the output cascoding device T.sub.4 is biased off the source of a transistor T.sub.5, instead of through direct connection with the gate of input cascoding device T.sub.3, as before. The connections between transistors T.sub.1 and T.sub.2 are made as in circuit 20; however, a voltage level shifter 31, comprising series-connected transistors T.sub.5 and T.sub.6, is interposed between transistors T.sub.3 and T.sub.4, as shown. Transistor T.sub.5 has its gate connected to the gate of diode-connected transistor T.sub.3 ; its source connected to the gate of transistor T.sub.4 ; and its drain connected to receive an additional reference current I.sub.A from a reference voltage terminal +V.sub.A. Transistor T.sub.6 has its source commonly connected to ground with the sources of transistors T.sub.1 and T.sub.2 ; its gate connected to the gates of diode-connected transistor T.sub.1 and transistor T.sub.2 ; and its drain connected to the source of transistor T.sub.5. Thus, assuming all operational parameters of transistors T.sub.1 through T.sub.6 are suitably chosen, the voltage level shifter 31 comprised of series-connected transistors T.sub.5 and T.sub.6, will flow a current I.sub.A which mirrors the current I.sub.IN flowing through the series connection of transistors T.sub.1 and T.sub.3. The voltage potential at the source of transistor T.sub.5 will thus be similar to the voltage potential at the source of transistor T.sub.4 of circuit 20; thereby lowering the minimum voltage required to keep transistor T.sub.4 of circuit 30 in the saturated region. Because the voltage at the gate of transistor T.sub.4 in circuit 30 has been systematically "shifted" below the gate voltage of transistor T.sub.4 in circuit 20 (now applied as the gate voltage of transistor T.sub.5 in circuit 30) by an amount .DELTA.V=V.sub.GS5 (typically 1-2 volts), the mirror can maintain high output resistance while swinging substantially closer to the power supply. To prevent driving the output rail device T.sub.2 into the linear region, transistor T.sub.3 can be made somewhat longer to increase the gate voltages of transistors T.sub.3 and T.sub.5. With appropriate sizing, transistor T.sub.3 can set the drain voltage of transistor T.sub.2 to below 0.25 volts.
Unfortunately, because of the diode connections of transistors T.sub.1 and T.sub.3 and insertion of the voltage shifter 31 in circuit 30, second order variations in the drain-to-source voltages of the mirroring components will adversely vary the fixed relationship of I.sub.OUT /I.sub.IN for AC noise components on the DC input power supply. Because the drain voltages of the input rail device T.sub.1 and the output rail device T.sub.2 are no longer equal, the current gain is no longer precisely determined strictly by the ratio of device sizes, and influences due to the lambda effect must now be considered. The problem with the lambda effect is particularly severe with new small geometry processes (with short channel lengths), wherein the device output resistance is quite low. Similarly, the lack of symmetry looking up into the mirror from the power supply (unequal drain voltages and unequal impedances seen at the drains) causes the power supply rejection to be poor.
To date, the problem of simultaneously achieving the strict current gain, good power supply rejection and good output voltage swing has had no good solution. One proposed solution is disclosed in Babanezhad and Gregorian in the December, 1987, IEEE Journal of Solid-State Circuits (BG1082). This arrangement, however, requires two identical input currents, which is undesirable.